/*********************************************************
	Project:	cap4
	File name:	st79.h
	Description:	
	Write/Modify:	milo zhong
	Time:		2007-9-14
*********************************************************/

//port A
ext volatile UCharField U_PA_ODR @0x5000;//Port A output data register
ext volatile UCharField U_PA_IDR @0x5001;//Port A pin input register
ext volatile UCharField U_PA_DDR @0x5002;//Port A data direction register
ext volatile UCharField U_PA_CR1 @0x5003;//Port A control register 1
ext volatile UCharField U_PA_CR2 @0x5004;//Port A control register 2
#define	PA_ODR				     U_PA_ODR.byte
#define	PA_ODR0                         U_PA_ODR.field.B0
#define 	PA_ODR1                         U_PA_ODR.field.B1
#define 	PA_ODR2                         U_PA_ODR.field.B2
#define 	PA_ODR3                         U_PA_ODR.field.B3
#define 	PA_ODR4                         U_PA_ODR.field.B4
#define 	PA_ODR5                         U_PA_ODR.field.B5
#define 	PA_ODR6                         U_PA_ODR.field.B6
#define 	PA_ODR7                         U_PA_ODR.field.B7

#define 	PA_IDR                           U_PA_IDR.byte
#define 	PA_IDR0                         U_PA_IDR.field.B0
#define 	PA_IDR1                         U_PA_IDR.field.B1
#define 	PA_IDR2                         U_PA_IDR.field.B2
#define 	PA_IDR3                         U_PA_IDR.field.B3
#define 	PA_IDR4                         U_PA_IDR.field.B4
#define 	PA_IDR5                         U_PA_IDR.field.B5
#define 	PA_IDR6                         U_PA_IDR.field.B6
#define PA_IDR7                           U_PA_IDR.field.B7



#define	PA_DDR				   U_PA_DDR.byte
#define 	PA_DDR0                         U_PA_DDR.field.B0
#define 	PA_DDR1                         U_PA_DDR.field.B1
#define 	PA_DDR2                         U_PA_DDR.field.B2
#define 	PA_DDR3                         U_PA_DDR.field.B3
#define 	PA_DDR4                         U_PA_DDR.field.B4
#define	 PA_DDR5                         U_PA_DDR.field.B5
#define 	PA_DDR6                         U_PA_DDR.field.B6
#define 	PA_DDR7                         U_PA_DDR.field.B7

#define	PA_CR1				   U_PA_CR1.byte
#define 	PA_CR10                         U_PA_CR1.field.B0
#define 	PA_CR11                         U_PA_CR1.field.B1
#define PA_CR12                         U_PA_CR1.field.B2
#define PA_CR13                         U_PA_CR1.field.B3
#define PA_CR14                         U_PA_CR1.field.B4
#define PA_CR15                         U_PA_CR1.field.B5
#define PA_CR16                         U_PA_CR1.field.B6
#define PA_CR17                         U_PA_CR1.field.B7

#define	PA_CR2				   U_PA_CR2.byte
#define PA_CR20                         U_PA_CR2.field.B0
#define PA_CR21                         U_PA_CR2.field.B1
#define PA_CR22                         U_PA_CR2.field.B2
#define PA_CR23                         U_PA_CR2.field.B3
#define PA_CR24                         U_PA_CR2.field.B4
#define PA_CR25                         U_PA_CR2.field.B5
#define PA_CR26                         U_PA_CR2.field.B6
#define PA_CR27                         U_PA_CR2.field.B7


//port B
ext volatile UCharField U_PB_ODR @0x5005;
ext volatile UCharField U_PB_IDR @0x5006;
ext volatile UCharField U_PB_DDR @0x5007;
ext volatile UCharField U_PB_CR1 @0x5008;
ext volatile UCharField U_PB_CR2 @0x5009;
#define	PB_ODR				U_PB_ODR.byte
#define PB_ODR0                         U_PB_ODR.field.B0
#define PB_ODR1                         U_PB_ODR.field.B1
#define PB_ODR2                         U_PB_ODR.field.B2
#define PB_ODR3                         U_PB_ODR.field.B3
#define PB_ODR4                         U_PB_ODR.field.B4
#define PB_ODR5                         U_PB_ODR.field.B5
#define PB_ODR6                         U_PB_ODR.field.B6
#define PB_ODR7                         U_PB_ODR.field.B7

#define PB_IDR                          U_PB_IDR.byte
#define PB_IDR0                         U_PB_IDR.field.B0
#define PB_IDR1                         U_PB_IDR.field.B1
#define PB_IDR2                         U_PB_IDR.field.B2
#define PB_IDR3                         U_PB_IDR.field.B3
#define PB_IDR4                         U_PB_IDR.field.B4
#define PB_IDR5                         U_PB_IDR.field.B5
#define PB_IDR6                         U_PB_IDR.field.B6
#define PB_IDR7                         U_PB_IDR.field.B7

#define	PB_DDR				U_PB_DDR.byte
#define PB_DDR0                         U_PB_DDR.field.B0
#define PB_DDR1                         U_PB_DDR.field.B1
#define PB_DDR2                         U_PB_DDR.field.B2
#define PB_DDR3                         U_PB_DDR.field.B3
#define PB_DDR4                         U_PB_DDR.field.B4
#define PB_DDR5                         U_PB_DDR.field.B5
#define PB_DDR6                         U_PB_DDR.field.B6
#define PB_DDR7                         U_PB_DDR.field.B7

#define	PB_CR1				U_PB_CR1.byte
#define PB_CR10                         U_PB_CR1.field.B0
#define PB_CR11                         U_PB_CR1.field.B1
#define PB_CR12                         U_PB_CR1.field.B2
#define PB_CR13                         U_PB_CR1.field.B3
#define PB_CR14                         U_PB_CR1.field.B4
#define PB_CR15                         U_PB_CR1.field.B5
#define PB_CR16                         U_PB_CR1.field.B6
#define PB_CR17                         U_PB_CR1.field.B7

#define	PB_CR2				U_PB_CR2.byte
#define PB_CR20                         U_PB_CR2.field.B0
#define PB_CR21                         U_PB_CR2.field.B1
#define PB_CR22                         U_PB_CR2.field.B2
#define PB_CR23                         U_PB_CR2.field.B3
#define PB_CR24                         U_PB_CR2.field.B4
#define PB_CR25                         U_PB_CR2.field.B5
#define PB_CR26                         U_PB_CR2.field.B6
#define PB_CR27                         U_PB_CR2.field.B7
//port C
ext volatile UCharField U_PC_ODR @0x500A;
ext volatile UCharField U_PC_IDR @0x500B;
ext volatile UCharField U_PC_DDR @0x500C;
ext volatile UCharField U_PC_CR1 @0x500D;
ext volatile UCharField U_PC_CR2 @0x500E;
#define	PC_ODR				U_PC_ODR.byte
#define PC_ODR0                         U_PC_ODR.field.B0
#define PC_ODR1                         U_PC_ODR.field.B1
#define PC_ODR2                         U_PC_ODR.field.B2
#define PC_ODR3                         U_PC_ODR.field.B3
#define PC_ODR4                         U_PC_ODR.field.B4
#define PC_ODR5                         U_PC_ODR.field.B5
#define PC_ODR6                         U_PC_ODR.field.B6
#define PC_ODR7                         U_PC_ODR.field.B7

#define PC_IDR                          U_PC_IDR.byte
#define PC_IDR0                         U_PC_IDR.field.B0
#define PC_IDR1                         U_PC_IDR.field.B1
#define PC_IDR2                         U_PC_IDR.field.B2
#define PC_IDR3                         U_PC_IDR.field.B3
#define PC_IDR4                         U_PC_IDR.field.B4
#define PC_IDR5                         U_PC_IDR.field.B5
#define PC_IDR6                         U_PC_IDR.field.B6
#define PC_IDR7                         U_PC_IDR.field.B7

#define	PC_DDR				U_PC_DDR.byte
#define PC_DDR0                         U_PC_DDR.field.B0
#define PC_DDR1                         U_PC_DDR.field.B1
#define PC_DDR2                         U_PC_DDR.field.B2
#define PC_DDR3                         U_PC_DDR.field.B3
#define PC_DDR4                         U_PC_DDR.field.B4
#define PC_DDR5                         U_PC_DDR.field.B5
#define PC_DDR6                         U_PC_DDR.field.B6
#define PC_DDR7                         U_PC_DDR.field.B7

#define	PC_CR1				U_PC_CR1.byte
#define PC_CR10                         U_PC_CR1.field.B0
#define PC_CR11                         U_PC_CR1.field.B1
#define PC_CR12                         U_PC_CR1.field.B2
#define PC_CR13                         U_PC_CR1.field.B3
#define PC_CR14                         U_PC_CR1.field.B4
#define PC_CR15                         U_PC_CR1.field.B5
#define PC_CR16                         U_PC_CR1.field.B6
#define PC_CR17                         U_PC_CR1.field.B7

#define PC_CR2				  U_PC_CR2.byte
#define PC_CR20                         U_PC_CR2.field.B0
#define PC_CR21                         U_PC_CR2.field.B1
#define PC_CR22                         U_PC_CR2.field.B2
#define PC_CR23                         U_PC_CR2.field.B3
#define PC_CR24                         U_PC_CR2.field.B4
#define PC_CR25                         U_PC_CR2.field.B5
#define PC_CR26                         U_PC_CR2.field.B6
#define PC_CR27                         U_PC_CR2.field.B7
//port D
ext volatile UCharField U_PD_ODR @0x500F;
ext volatile UCharField U_PD_IDR @0x5010;
ext volatile UCharField U_PD_DDR @0x5011;
ext volatile UCharField U_PD_CR1 @0x5012;
ext volatile UCharField U_PD_CR2 @0x5013;
#define PD_ODR				   U_PD_ODR.byte
#define PD_ODR0                         U_PD_ODR.field.B0
#define PD_ODR1                         U_PD_ODR.field.B1
#define PD_ODR2                         U_PD_ODR.field.B2
#define PD_ODR3                         U_PD_ODR.field.B3
#define PD_ODR4                         U_PD_ODR.field.B4
#define PD_ODR5                         U_PD_ODR.field.B5
#define PD_ODR6                         U_PD_ODR.field.B6
#define PD_ODR7                         U_PD_ODR.field.B7

#define PD_IDR                           U_PD_IDR.byte
#define PD_IDR0                         U_PD_IDR.field.B0
#define PD_IDR1                         U_PD_IDR.field.B1
#define PD_IDR2                         U_PD_IDR.field.B2
#define PD_IDR3                         U_PD_IDR.field.B3
#define PD_IDR4                         U_PD_IDR.field.B4
#define PD_IDR5                         U_PD_IDR.field.B5
#define PD_IDR6                         U_PD_IDR.field.B6
#define PD_IDR7                         U_PD_IDR.field.B7

#define PD_DDR				   U_PD_DDR.byte
#define PD_DDR0                         U_PD_DDR.field.B0
#define PD_DDR1                         U_PD_DDR.field.B1
#define PD_DDR2                         U_PD_DDR.field.B2
#define PD_DDR3                         U_PD_DDR.field.B3
#define PD_DDR4                         U_PD_DDR.field.B4
#define PD_DDR5                         U_PD_DDR.field.B5
#define PD_DDR6                         U_PD_DDR.field.B6
#define PD_DDR7                         U_PD_DDR.field.B7

#define PD_CR1				  U_PD_CR1.byte
#define PD_CR10                         U_PD_CR1.field.B0
#define PD_CR11                         U_PD_CR1.field.B1
#define PD_CR12                         U_PD_CR1.field.B2
#define PD_CR13                         U_PD_CR1.field.B3
#define PD_CR14                         U_PD_CR1.field.B4
#define PD_CR15                         U_PD_CR1.field.B5
#define PD_CR16                         U_PD_CR1.field.B6
#define PD_CR17                         U_PD_CR1.field.B7

#define PD_CR2				  U_PD_CR2.byte
#define PD_CR20                         U_PD_CR2.field.B0
#define PD_CR21                         U_PD_CR2.field.B1
#define PD_CR22                         U_PD_CR2.field.B2
#define PD_CR23                         U_PD_CR2.field.B3
#define PD_CR24                         U_PD_CR2.field.B4
#define PD_CR25                         U_PD_CR2.field.B5
#define PD_CR26                         U_PD_CR2.field.B6
#define PD_CR27                         U_PD_CR2.field.B7

//port E
ext volatile UCharField U_PE_ODR @0x5014;
ext volatile UCharField U_PE_IDR @0x5015;
ext volatile UCharField U_PE_DDR @0x5016;
ext volatile UCharField U_PE_CR1 @0x5017;
ext volatile UCharField U_PE_CR2 @0x5018;
#define	PE_ODR				U_PE_ODR.byte
#define PE_ODR0                         U_PE_ODR.field.B0
#define PE_ODR1                         U_PE_ODR.field.B1
#define PE_ODR2                         U_PE_ODR.field.B2
#define PE_ODR3                         U_PE_ODR.field.B3
#define PE_ODR4                         U_PE_ODR.field.B4
#define PE_ODR5                         U_PE_ODR.field.B5
#define PE_ODR6                         U_PE_ODR.field.B6
#define PE_ODR7                         U_PE_ODR.field.B7

#define PE_IDR                          U_PE_IDR.byte
#define PE_IDR0                         U_PE_IDR.field.B0
#define PE_IDR1                         U_PE_IDR.field.B1
#define PE_IDR2                         U_PE_IDR.field.B2
#define PE_IDR3                         U_PE_IDR.field.B3
#define PE_IDR4                         U_PE_IDR.field.B4
#define PE_IDR5                         U_PE_IDR.field.B5
#define PE_IDR6                         U_PE_IDR.field.B6
#define PE_IDR7                         U_PE_IDR.field.B7

#define	PE_DDR				U_PE_DDR.byte
#define PE_DDR0                         U_PE_DDR.field.B0
#define PE_DDR1                         U_PE_DDR.field.B1
#define PE_DDR2                         U_PE_DDR.field.B2
#define PE_DDR3                         U_PE_DDR.field.B3
#define PE_DDR4                         U_PE_DDR.field.B4
#define PE_DDR5                         U_PE_DDR.field.B5
#define PE_DDR6                         U_PE_DDR.field.B6
#define PE_DDR7                         U_PE_DDR.field.B7

#define	PE_CR1				U_PE_CR1.byte
#define PE_CR10                         U_PE_CR1.field.B0
#define PE_CR11                         U_PE_CR1.field.B1
#define PE_CR12                         U_PE_CR1.field.B2
#define PE_CR13                         U_PE_CR1.field.B3
#define PE_CR14                         U_PE_CR1.field.B4
#define PE_CR15                         U_PE_CR1.field.B5
#define PE_CR16                         U_PE_CR1.field.B6
#define PE_CR17                         U_PE_CR1.field.B7

#define	PE_CR2				U_PE_CR2.byte
#define PE_CR20                         U_PE_CR2.field.B0
#define PE_CR21                         U_PE_CR2.field.B1
#define PE_CR22                         U_PE_CR2.field.B2
#define PE_CR23                         U_PE_CR2.field.B3
#define PE_CR24                         U_PE_CR2.field.B4
#define PE_CR25                         U_PE_CR2.field.B5
#define PE_CR26                         U_PE_CR2.field.B6
#define PE_CR27                         U_PE_CR2.field.B7
//port F
ext volatile UCharField U_PF_ODR @0x5019;
ext volatile UCharField U_PF_IDR @0x501A;
ext volatile UCharField U_PF_DDR @0x501B;
ext volatile UCharField U_PF_CR1 @0x501C;
ext volatile UCharField U_PF_CR2 @0x501D;
#define	PF_ODR				U_PF_ODR.byte
#define PF_ODR0                         U_PF_ODR.field.B0
#define PF_ODR1                         U_PF_ODR.field.B1
#define PF_ODR2                         U_PF_ODR.field.B2
#define PF_ODR3                         U_PF_ODR.field.B3
#define PF_ODR4                         U_PF_ODR.field.B4
#define PF_ODR5                         U_PF_ODR.field.B5
#define PF_ODR6                         U_PF_ODR.field.B6
#define PF_ODR7                         U_PF_ODR.field.B7

#define PF_IDR                          U_PF_IDR.byte
#define PF_IDR0                         U_PF_IDR.field.B0
#define PF_IDR1                         U_PF_IDR.field.B1
#define PF_IDR2                         U_PF_IDR.field.B2
#define PF_IDR3                         U_PF_IDR.field.B3
#define PF_IDR4                         U_PF_IDR.field.B4
#define PF_IDR5                         U_PF_IDR.field.B5
#define PF_IDR6                         U_PF_IDR.field.B6
#define PF_IDR7                         U_PF_IDR.field.B7

#define	PF_DDR				U_PF_DDR.byte
#define PF_DDR0                         U_PF_DDR.field.B0
#define PF_DDR1                         U_PF_DDR.field.B1
#define PF_DDR2                         U_PF_DDR.field.B2
#define PF_DDR3                         U_PF_DDR.field.B3
#define PF_DDR4                         U_PF_DDR.field.B4
#define PF_DDR5                         U_PF_DDR.field.B5
#define PF_DDR6                         U_PF_DDR.field.B6
#define PF_DDR7                         U_PF_DDR.field.B7

#define	PF_CR1				U_PF_CR1.byte
#define PF_CR10                         U_PF_CR1.field.B0
#define PF_CR11                         U_PF_CR1.field.B1
#define PF_CR12                         U_PF_CR1.field.B2
#define PF_CR13                         U_PF_CR1.field.B3
#define PF_CR14                         U_PF_CR1.field.B4
#define PF_CR15                         U_PF_CR1.field.B5
#define PF_CR16                         U_PF_CR1.field.B6
#define PF_CR17                         U_PF_CR1.field.B7

#define	PF_CR2				U_PF_CR2.byte
#define PF_CR20                         U_PF_CR2.field.B0
#define PF_CR21                         U_PF_CR2.field.B1
#define PF_CR22                         U_PF_CR2.field.B2
#define PF_CR23                         U_PF_CR2.field.B3
#define PF_CR24                         U_PF_CR2.field.B4
#define PF_CR25                         U_PF_CR2.field.B5
#define PF_CR26                         U_PF_CR2.field.B6
#define PF_CR27                         U_PF_CR2.field.B7
//port G
ext volatile UCharField U_PG_ODR @0x501E;
ext volatile UCharField U_PG_IDR @0x501F;
ext volatile UCharField U_PG_DDR @0x5020;
ext volatile UCharField U_PG_CR1 @0x5021;
ext volatile UCharField U_PG_CR2 @0x5022;
#define	PG_ODR				U_PG_ODR.byte
#define PG_ODR0                         U_PG_ODR.field.B0
#define PG_ODR1                         U_PG_ODR.field.B1
#define PG_ODR2                         U_PG_ODR.field.B2
#define PG_ODR3                         U_PG_ODR.field.B3
#define PG_ODR4                         U_PG_ODR.field.B4
#define PG_ODR5                         U_PG_ODR.field.B5
#define PG_ODR6                         U_PG_ODR.field.B6
#define PG_ODR7                         U_PG_ODR.field.B7

#define PG_IDR                          U_PG_IDR.byte
#define PG_IDR0                         U_PG_IDR.field.B0
#define PG_IDR1                         U_PG_IDR.field.B1
#define PG_IDR2                         U_PG_IDR.field.B2
#define PG_IDR3                         U_PG_IDR.field.B3
#define PG_IDR4                         U_PG_IDR.field.B4
#define PG_IDR5                         U_PG_IDR.field.B5
#define PG_IDR6                         U_PG_IDR.field.B6
#define PG_IDR7                         U_PG_IDR.field.B7

#define	PG_DDR				U_PG_DDR.byte
#define PG_DDR0                         U_PG_DDR.field.B0
#define PG_DDR1                         U_PG_DDR.field.B1
#define PG_DDR2                         U_PG_DDR.field.B2
#define PG_DDR3                         U_PG_DDR.field.B3
#define PG_DDR4                         U_PG_DDR.field.B4
#define PG_DDR5                         U_PG_DDR.field.B5
#define PG_DDR6                         U_PG_DDR.field.B6
#define PG_DDR7                         U_PG_DDR.field.B7


#define	PG_CR1				U_PG_CR1.byte
#define PG_CR10                         U_PG_CR1.field.B0
#define PG_CR11                         U_PG_CR1.field.B1
#define PG_CR12                         U_PG_CR1.field.B2
#define PG_CR13                         U_PG_CR1.field.B3
#define PG_CR14                         U_PG_CR1.field.B4
#define PG_CR15                         U_PG_CR1.field.B5
#define PG_CR16                         U_PG_CR1.field.B6
#define PG_CR17                         U_PG_CR1.field.B7

#define	PG_CR2				U_PG_CR2.byte
#define PG_CR20                         U_PG_CR2.field.B0
#define PG_CR21                         U_PG_CR2.field.B1
#define PG_CR22                         U_PG_CR2.field.B2
#define PG_CR23                         U_PG_CR2.field.B3
#define PG_CR24                         U_PG_CR2.field.B4
#define PG_CR25                         U_PG_CR2.field.B5
#define PG_CR26                         U_PG_CR2.field.B6
#define PG_CR27                         U_PG_CR2.field.B7
//port H
ext volatile UCharField U_PH_ODR @0x5023;
ext volatile UCharField U_PH_IDR @0x5024;
ext volatile UCharField U_PH_DDR @0x5025;
ext volatile UCharField U_PH_CR1 @0x5026;
ext volatile UCharField U_PH_CR2 @0x5027;
#define	PH_ODR				U_PH_ODR.byte
#define PH_ODR0                         U_PH_ODR.field.B0
#define PH_ODR1                         U_PH_ODR.field.B1
#define PH_ODR2                         U_PH_ODR.field.B2
#define PH_ODR3                         U_PH_ODR.field.B3
#define PH_ODR4                         U_PH_ODR.field.B4
#define PH_ODR5                         U_PH_ODR.field.B5
#define PH_ODR6                         U_PH_ODR.field.B6
#define PH_ODR7                         U_PH_ODR.field.B7

#define PH_IDR                          U_PH_IDR.byte
#define PH_IDR0                         U_PH_IDR.field.B0
#define PH_IDR1                         U_PH_IDR.field.B1
#define PH_IDR2                         U_PH_IDR.field.B2
#define PH_IDR3                         U_PH_IDR.field.B3
#define PH_IDR4                         U_PH_IDR.field.B4
#define PH_IDR5                         U_PH_IDR.field.B5
#define PH_IDR6                         U_PH_IDR.field.B6
#define PH_IDR7                         U_PH_IDR.field.B7

#define	PH_DDR				U_PH_DDR.byte
#define PH_DDR0                         U_PH_DDR.field.B0
#define PH_DDR1                         U_PH_DDR.field.B1
#define PH_DDR2                         U_PH_DDR.field.B2
#define PH_DDR3                         U_PH_DDR.field.B3
#define PH_DDR4                         U_PH_DDR.field.B4
#define PH_DDR5                         U_PH_DDR.field.B5
#define PH_DDR6                         U_PH_DDR.field.B6
#define PH_DDR7                         U_PH_DDR.field.B7

#define	PH_CR1				U_PH_CR1.byte
#define PH_CR10                         U_PH_CR1.field.B0
#define PH_CR11                         U_PH_CR1.field.B1
#define PH_CR12                         U_PH_CR1.field.B2
#define PH_CR13                         U_PH_CR1.field.B3
#define PH_CR14                         U_PH_CR1.field.B4
#define PH_CR15                         U_PH_CR1.field.B5
#define PH_CR16                         U_PH_CR1.field.B6
#define PH_CR17                         U_PH_CR1.field.B7

#define	PH_CR2				U_PH_CR2.byte
#define PH_CR20                         U_PH_CR2.field.B0
#define PH_CR21                         U_PH_CR2.field.B1
#define PH_CR22                         U_PH_CR2.field.B2
#define PH_CR23                         U_PH_CR2.field.B3
#define PH_CR24                         U_PH_CR2.field.B4
#define PH_CR25                         U_PH_CR2.field.B5
#define PH_CR26                         U_PH_CR2.field.B6
#define PH_CR27                         U_PH_CR2.field.B7

//port I
ext volatile UCharField U_PI_ODR @0x5028;
ext volatile UCharField U_PI_IDR @0x5029;
ext volatile UCharField U_PI_DDR @0x502A;
ext volatile UCharField U_PI_CR1 @0x502B;
ext volatile UCharField U_PI_CR2 @0x502C;
#define	PI_ODR				U_PI_ODR.byte
#define PI_ODR0                         U_PI_ODR.field.B0
#define PI_ODR1                         U_PI_ODR.field.B1
#define PI_ODR2                         U_PI_ODR.field.B2
#define PI_ODR3                         U_PI_ODR.field.B3
#define PI_ODR4                         U_PI_ODR.field.B4
#define PI_ODR5                         U_PI_ODR.field.B5
#define PI_ODR6                         U_PI_ODR.field.B6
#define PI_ODR7                         U_PI_ODR.field.B7

#define PI_IDR                          U_PI_IDR.byte
#define PI_IDR0                         U_PI_IDR.field.B0
#define PI_IDR1                         U_PI_IDR.field.B1
#define PI_IDR2                         U_PI_IDR.field.B2
#define PI_IDR3                         U_PI_IDR.field.B3
#define PI_IDR4                         U_PI_IDR.field.B4
#define PI_IDR5                         U_PI_IDR.field.B5
#define PI_IDR6                         U_PI_IDR.field.B6
#define PI_IDR7                         U_PI_IDR.field.B7

#define	PI_DDR				U_PI_DDR.byte
#define PI_DDR0                         U_PI_DDR.field.B0
#define PI_DDR1                         U_PI_DDR.field.B1
#define PI_DDR2                         U_PI_DDR.field.B2
#define PI_DDR3                         U_PI_DDR.field.B3
#define PI_DDR4                         U_PI_DDR.field.B4
#define PI_DDR5                         U_PI_DDR.field.B5
#define PI_DDR6                         U_PI_DDR.field.B6
#define PI_DDR7                         U_PI_DDR.field.B7

#define	PI_CR1				U_PI_CR1.byte
#define PI_CR10                         U_PI_CR1.field.B0
#define PI_CR11                         U_PI_CR1.field.B1
#define PI_CR12                         U_PI_CR1.field.B2
#define PI_CR13                         U_PI_CR1.field.B3
#define PI_CR14                         U_PI_CR1.field.B4
#define PI_CR15                         U_PI_CR1.field.B5
#define PI_CR16                         U_PI_CR1.field.B6
#define PI_CR17                         U_PI_CR1.field.B7

#define	PI_CR2				U_PI_CR2.byte
#define 	PI_CR20                         U_PI_CR2.field.B0
#define	 PI_CR21                         	U_PI_CR2.field.B1
#define 	PI_CR22                         U_PI_CR2.field.B2
#define 	PI_CR23                         U_PI_CR2.field.B3
#define 	PI_CR24                         U_PI_CR2.field.B4
#define 	PI_CR25                         U_PI_CR2.field.B5
#define 	PI_CR26                         U_PI_CR2.field.B6
#define 	PI_CR27                         U_PI_CR2.field.B7
//Flash
ext volatile UCharField U_FLASH_CR1 @0x505A;//Flash control register 1
ext volatile UCharField U_FLASH_CR2 @0x505B;//Flash control register 2
ext volatile UCharField U_FLASH_NCR2 @0x505C;//Flash complementary control register
ext volatile UCharField U_FLASH_FPR @0x505D;//Flash protection register
ext volatile UCharField U_FLASH_NFPR @0x505E;//Flash complementary protection register
ext volatile UCharField U_FLASH_IAPSR @0x505F;//Flash in-application programming status register
ext volatile UCharField U_FLASH_PUKR @0x5062;//Flash program memory unprotection key register
ext volatile UCharField U_FLASH_DUKR @0x5064;//Data EEPROM unprotection register
#define 	FLASH_CR1                      U_FLASH_CR1.byte
#define 	FLASH_CR2                      U_FLASH_CR2.byte
#define 	FLASH_NCR2                     U_FLASH_NCR2.byte
#define 	FLASH_FPR                      U_FLASH_FPR.byte
#define 	FLASH_NFPR                     U_FLASH_NFPR.byte
#define 	FLASH_IAPSR                    U_FLASH_IAPSR.byte
#define 	FLASH_PUKR                     U_FLASH_PUKR.byte
#define 	FLASH_DUKR                     U_FLASH_DUKR.byte



//Opt
ext volatile UCharField U_OPT2 @0x5067;
ext volatile UCharField U_NOPT2 @0x5068;
ext volatile UCharField U_OPT3 @0x5069;
ext volatile UCharField U_NOPT3 @0x506A;
ext volatile UCharField U_OPT4 @0x506B;
ext volatile UCharField U_NOPT4 @0x506C;
ext volatile UCharField U_OPT5 @0x506D;
ext volatile UCharField U_NOPT5 @0x506E;
ext volatile UCharField U_OPT6 @0x506F;
ext volatile UCharField U_NOPT6 @0x5070;
ext volatile UCharField U_OPT7 @0x5071;
ext volatile UCharField U_NOPT7 @0x5072;
#define OPT2                           U_OPT2.byte
#define NOPT2                          U_NOPT2.byte
#define OPT3                           U_OPT3.byte
#define NOPT3                          U_NOPT3.byte
#define OPT4                           U_OPT4.byte
#define NOPT4                          U_NOPT4.byte
#define OPT5                           U_OPT5.byte
#define NOPT5                          U_NOPT5.byte
#define OPT6                           U_OPT6.byte
#define NOPT6                          U_NOPT6.byte
#define OPT7                           U_OPT7.byte
#define NOPT7                          U_NOPT7.byte

ext volatile UCharField U_EXTI_CR1 @0x50A0;//external interrupt control register 1
ext volatile UCharField U_EXTI_CR2 @0x50A1;//external interrupt control register 2
#define EXTI_CR1                    U_EXTI_CR1.byte
#define EXTI_CR2                    U_EXTI_CR2.byte

//RST
ext volatile UCharField U_RST_SR @0x50B3;//Reset status register
#define RST_SR          U_RST_SR.byte
#define WWDGF			U_RST_SR.field.B0
#define IWDGF			U_RST_SR.field.B1
#define SWIMF			U_RST_SR.field.B3
#define EMCF			U_RST_SR.field.B4

//CLK
ext volatile UCharField U_CLK_ICKR @0x50C0;//Internal clock register
ext volatile UCharField U_CLK_ECKR @0x50C1;//external clock register
ext volatile UCharField U_CLK_CMSR @0x50C3;//Clock master status register
ext volatile UCharField U_CLK_SWR @0x50C4;//Clock master switch register
ext volatile UCharField U_CLK_SWCR @0x50C5;//Switch control register
ext volatile UCharField U_CLK_CKDIVR @0x50C6;//Clock divider register
ext volatile UCharField U_CLK_PCKENR1 @0x50C7;//Peripheral clock gating register 1
ext volatile UCharField U_CLK_CSSR @0x50C8;//Clock security system register
ext volatile UCharField U_CLK_CCOR @0x50C9;//Configurable clock output register
//ext volatile UCharField U_CLK_HSESTR @0x50CA;//HSE clock startup time register
ext volatile UCharField U_CLK_PCKENR2 @0x50CA;//Peripheral clock gating register 2
ext volatile UCharField U_CLK_CANCCR @0x50CB;
//ext volatile UCharField U_CLK_HSICALR @0x50CC;//HSI clock calibration register
ext volatile UCharField  U_CLK_HSITRIMR @0x50CC;
ext volatile UCharField  U_CLK_SWIMCCR @0x50CD;
//ext volatile UCharField U_CLK_NHSICALR @0x50CD;//Complementary HSI clock calibration register
//ext volatile UCharField U_CLK_HSITRIMR @0x50CE;//HSI clock calibration trimming register
#define CLK_ICKR                     U_CLK_ICKR.byte
#define CLK_ICKR_HSIEN               U_CLK_ICKR.field.B0  //High speed internal RC oscillator enable
#define CLK_ICKR_HSIRDY              U_CLK_ICKR.field.B1  //High speed internal oscillator ready
#define CLK_ICKR_FHW                 U_CLK_ICKR.field.B2  //Fast Wake-up from Active Halt/Halt mode
#define CLK_ICKR_LSIEN               U_CLK_ICKR.field.B3  //Low speed internal RC oscillator enable
#define CLK_ICKR_LSIRDY               U_CLK_ICKR.field.B4  //Low speed internal oscillator ready
#define CLK_ICKR_SHW                 U_CLK_ICKR.field.B5   //Slow Wake-up from Active Halt/Halt modes



#define CLK_ECKR                     U_CLK_ECKR.byte
#define CLK_ECKR_HSEEN               U_CLK_ECKR.field.B0  //High speed external crystal oscillator enable
#define CLK_ECKR_HSERDY              U_CLK_ECKR.field.B1  //High speed external crystal oscillator ready

#define CLK_CMSR                     U_CLK_CMSR.byte
#define CLK_SWR                      U_CLK_SWR.byte
#define CLK_SWCR                     U_CLK_SWCR.byte
#define CLK_SWCR_SWBSY               U_CLK_SWCR.field.B0  //Switch busy
#define CLK_SWCR_SWEN                U_CLK_SWCR.field.B1  //Switch start/stop
#define CLK_SWCR_SWIEN               U_CLK_SWCR.field.B2  //Clock switch interrupt enable
#define CLK_SWCR_SWIF                U_CLK_SWCR.field.B3  //Clock switch interrupt flag

#define CLK_CKDIVR                   U_CLK_CKDIVR.byte
#define CLK_PCKENR1                  U_CLK_PCKENR1.byte
#define CLK_CSSR                     U_CLK_CSSR.byte
#define CLK_CCOR                     U_CLK_CCOR.byte
//#define CLK_HSESTR                   U_CLK_HSESTR.byte
#define CLK_PCKENR2                  U_CLK_PCKENR2.byte
#define CLK_CANCCR			U_CLK_CANCCR.byte
//#define CLK_HSICALR                  U_CLK_HSICALR.byte
//#define CLK_NHSICALR                 U_CLK_NHSICALR.byte
#define CLK_HSITRIMR              U_CLK_HSITRIMR.byte
#define CLK_SWIMCCR			U_CLK_SWIMCCR.byte

//Window watchdog---WWDG
ext volatile UCharField U_WWDG_CR @0x50D1;//Control Register
ext volatile UCharField U_WWDG_WR @0x50D2;//Window Register
#define WWDG_CR                    U_WWDG_CR.byte
#define WWDG_WR                    U_WWDG_WR.byte

//Independent Watchdog (IWDG)
ext volatile UCharField U_IWDG_KR @0x50E0;//Key register
ext volatile UCharField U_IWDG_PR @0x50E1;//Prescaler register
ext volatile UCharField U_IWDG_RLR @0x50E2;//Reload register
#define IWDG_KR                    U_IWDG_KR.byte
#define IWDG_PR                    U_IWDG_PR.byte
#define IWDG_RLR                   U_IWDG_RLR.byte

//Auto Wake-up
ext volatile UCharField U_AWU_CSR1 @0x50F0;//Control/Status register
ext volatile UCharField U_AWU_APR  @0x50F1;//Asynchronous prescaler register
ext volatile UCharField U_AWU_TBR  @0x50F2;//Timebase selection register
ext volatile UCharField U_BEEP_CSR @0x50F3;//Control/Status register 2
#define AWU_CSR1                   U_AWU_CSR1.byte
#define AWU_APR                    U_AWU_APR.byte
#define AWU_TBR                    U_AWU_TBR.byte
#define BEEP_CSR                   U_BEEP_CSR.byte
#define AWUEN					   U_AWU_CSR1.field.B4
#define BEEPEN					   U_BEEP_CSR.field.B5

//Spi
ext volatile UCharField U_SPI_CR1 @0x5200;//SPI control register 1
ext volatile UCharField U_SPI_CR2 @0x5201;//SPI control register 2
ext volatile UCharField U_SPI_ICR @0x5202;//SPI Interrupt Control Register
ext volatile UCharField U_SPI_SR @0x5203;//SPI Status Register
ext volatile UCharField U_SPI_DR @0x5204;//SPI Data Register
ext volatile UCharField U_SPI_CRCPR @0x5205;//SPI CRC Polynomial Register
ext volatile UCharField U_SPI_RXCRCR @0x5206;//SPI Rx CRC Register
ext volatile UCharField U_SPI_TXCRCR @0x5207;//SPI Tx CRC Register
#define SPI_CR1                   U_SPI_CR1.byte
#define SPI_CR1_CPHA         U_SPI_CR1.field.B0 //Clock Phase
#define SPI_CR1_CPOL         U_SPI_CR1.field.B1 //Clock Polarity
#define SPI_CR1_MSTR         U_SPI_CR1.field.B2 //Master Selection
#define SPI_CR1_SPE           U_SPI_CR1.field.B6 //SPI Enable
#define SPI_CR1_LSBFIRST  U_SPI_CR1.field.B7 //Frame Format

#define SPI_CR2                   U_SPI_CR2.byte
#define SPI_CR2_SSI               U_SPI_CR2.field.B0  //Internal slave select;0: Slave,1: Master
#define SPI_CR2_SSM               U_SPI_CR2.field.B1  //Software slave management;0: disable,1: enable
#define SPI_CR2_RXONLY            U_SPI_CR2.field.B2  //Receive only;0: Full-duplex (Transmit and receive),1: Output disabled (Receive only mode)
#define SPI_CR2_CRCNEXT           U_SPI_CR2.field.B4  //Transmit CRC next;0: Next transmit value is from Tx buffer 1: Next transmit value is from Tx CRC register
#define SPI_CR2_CRCEN             U_SPI_CR2.field.B5  //Hardware CRC calculation enable,0: disable,1: enable
#define SPI_CR2_BDOE              U_SPI_CR2.field.B6  //Output enable in bi-directional mode;0:Output disabled,1:Output enabled
#define SPI_CR2_BDM               U_SPI_CR2.field.B7  //Bi-directional data mode enable;0:2-line uni-directional data mode,1:1-line bi-directional data mode

#define SPI_ICR                   U_SPI_ICR.byte
#define SPI_ICR_WKIE              U_SPI_ICR.field.B4 //Wake-up interrupt enable
#define SPI_ICR_ERRE              U_SPI_ICR.field.B5 //Error interrupt enable
#define SPI_ICR_RXIE              U_SPI_ICR.field.B6 //RX buffer not empty interrupt enable
#define SPI_ICR_TXIE              U_SPI_ICR.field.B7 //Tx buffer empty interrupt enable

#define SPI_SR                    U_SPI_SR.byte
#define SPI_SR_RxNE               U_SPI_SR.field.B0 //Receive buffer not empty,0: Rx buffer empty,1: Rx buffer not empty
#define SPI_SR_TXE                U_SPI_SR.field.B1 //Transmit buffer empty;0: Tx buffer not empty,1: Tx buffer empty
#define SPI_SR_WKUP               U_SPI_SR.field.B3 //Wake-up Flag;0 : No Wake-up occured,1: Wake-up event occurred
#define SPI_SR_CRCERR             U_SPI_SR.field.B4 //CRC error flag
#define SPI_SR_MODF               U_SPI_SR.field.B5 //Mode fault
#define SPI_SR_OVR                U_SPI_SR.field.B6 //Overrun flag
#define SPI_SR_BSY                U_SPI_SR.field.B7 //Busy flag

#define SPI_DR                    U_SPI_DR.byte
#define SPI_CRCPR                 U_SPI_CRCPR.byte
#define SPI_RXCRCR                U_SPI_RXCRCR.byte
#define SPI_TXCRCR                U_SPI_TXCRCR.byte

//I2C
ext volatile UCharField U_I2C_CR1 @0x5210;//Control register 1
ext volatile UCharField U_I2C_CR2 @0x5211;//Control register 2
ext volatile UCharField U_I2C_FREQR @0x5212;//Frequency register
ext volatile UCharField U_I2C_OARL @0x5213;//Own address register LSB
ext volatile UCharField U_I2C_OARH @0x5214;//Own address register MSB
ext volatile UCharField U_I2C_DR @0x5216;//Data register
ext volatile UCharField U_I2C_SR1 @0x5217;//Status register 1
ext volatile UCharField U_I2C_SR2 @0x5218;//Status register 2
ext volatile UCharField U_I2C_SR3 @0x5219;//Status register 3
ext volatile UCharField U_I2C_ITR @0x521A;//Interrupt register
ext volatile UCharField U_I2C_CCRL @0x521B;//Clock control register low
ext volatile UCharField U_I2C_CCRH @0x521C;//Clock control register High
ext volatile UCharField U_I2C_TRISER @0x521D;//TRISE Register
ext volatile UCharField U_I2C_PECR @0x521E;//Packet Error Checking Register
#define I2C_CR1                   U_I2C_CR1.byte
#define I2C_CR1_PE                U_I2C_CR1.field.B0
#define I2C_CR1_ENGC              U_I2C_CR1.field.B6
#define I2C_CR1_NOSTRETCH         U_I2C_CR1.field.B7

#define I2C_CR2                   U_I2C_CR2.byte
#define I2C_CR2_START             U_I2C_CR2.field.B0
#define I2C_CR2_STOP              U_I2C_CR2.field.B1
#define I2C_CR2_ACK               U_I2C_CR2.field.B2
#define I2C_CR2_POS               U_I2C_CR2.field.B3
#define I2C_CR2_SWRST             U_I2C_CR2.field.B7


#define I2C_FREQR                 U_I2C_FREQR.byte
#define I2C_OARL                  U_I2C_OARL.byte
#define I2C_OARH                  U_I2C_OARH.byte
#define I2C_OARH_ADDMODE          U_I2C_OARH.field.B7

#define I2C_DR                    U_I2C_DR.byte

#define I2C_SR1                   U_I2C_SR1.byte     //READ ONLY
#define I2C_SR1_SB                U_I2C_SR1.field.B0   //Start Bit (Master mode)
#define I2C_SR1_ADDR              U_I2C_SR1.field.B1  //Address sent (master mode)/matched (slave mode)
#define I2C_SR1_BTF               U_I2C_SR1.field.B2  //Byte Transfer Finished
#define I2C_SR1_ADD10             U_I2C_SR1.field.B3  //10-bit header sent (Master mode)
#define I2C_SR1_STOPF             U_I2C_SR1.field.B4  //Stop detection (Slave mode)
#define I2C_SR1_RxNE              U_I2C_SR1.field.B6  //Data Register not Empty (receivers)
#define I2C_SR1_TxE               U_I2C_SR1.field.B7  //Data Register Empty (transmitters)


#define I2C_SR2                   U_I2C_SR2.byte      //READ ONLY
#define I2C_SR2_BERR              U_I2C_SR2.field.B0 //Bus Error
#define I2C_SR2_ARLO              U_I2C_SR2.field.B1  //Arbitration Lost (master mode)
#define I2C_SR2_AF                U_I2C_SR2.field.B2  //Acknowledge Failure.
#define I2C_SR2_OVR               U_I2C_SR2.field.B3  //Overrun/Underrun
#define I2C_SR2_WUFH              U_I2C_SR2.field.B5   //Wake-up from Halt

#define I2C_SR3                   U_I2C_SR3.byte //READ ONLY
#define I2C_SR3_MSL               U_I2C_SR3.field.B0 //Master/Slave
#define I2C_SR3_BUSY              U_I2C_SR3.field.B1 //Bus Busy
#define I2C_SR3_TRA               U_I2C_SR3.field.B2 //Transmitter/Receiver
#define I2C_SR3_GENCALL           U_I2C_SR3.field.B4 //General Call Header (Slave mode)

#define I2C_ITR                   U_I2C_ITR.byte
#define I2C_ITR_ITERREN           U_I2C_ITR.field.B0  //Error Interrupt Enable
#define I2C_ITR_ITEVTEN           U_I2C_ITR.field.B1 //Event Interrupt Enable
#define I2C_ITR_ITBUFEN           U_I2C_ITR.field.B2 //Buffer Interrupt Enable

#define I2C_CCRL                  U_I2C_CCRL.byte
#define I2C_CCRH                  U_I2C_CCRH.byte
#define I2C_TRISER                U_I2C_TRISER.byte
#define I2C_PECR                  U_I2C_PECR.byte


//Usart
ext volatile UCharField U_USART_SR @0x5230;//Status Register
ext volatile UCharField U_USART_DR @0x5231;//Data Register
ext volatile UCharField U_USART_BRR1 @0x5232;//Baud Rate Register 1
ext volatile UCharField U_USART_BRR2 @0x5233;//Baud Rate Register 2
ext volatile UCharField U_USART_CR1 @0x5234;//Control Register 1
ext volatile UCharField U_USART_CR2 @0x5235;//Control Register 2
ext volatile UCharField U_USART_CR3 @0x5236;//Control Register 3
ext volatile UCharField U_USART_CR4 @0x5237;//Control Register 4
ext volatile UCharField U_USART_CR5 @0x5238;//Control Register 5 
ext volatile UCharField U_USART_GTR @0x5239;//Guard time register
ext volatile UCharField U_USART_PSCR @0x523A;//Prescaler register
#define USART_SR                   U_USART_SR.byte
#define USART_DR                   U_USART_DR.byte
#define USART_BRR1                 U_USART_BRR1.byte
#define USART_BRR2                 U_USART_BRR2.byte
#define USART_CR1                  U_USART_CR1.byte
#define USART_CR2                  U_USART_CR2.byte
#define USART_CR3                  U_USART_CR3.byte
#define USART_CR4                  U_USART_CR4.byte
#define USART_CR5                  U_USART_CR5.byte
#define USART_GTR                  U_USART_GTR.byte
#define USART_PSCR                 U_USART_PSCR.byte

//Linuart
ext volatile UCharField U_LINUART_SR @0x5240;//Status Register
ext volatile UCharField U_LINUART_DR @0x5241;//Data Register
ext volatile UCharField U_LINUART_BRR1 @0x5242;//Baud Rate Register 1
ext volatile UCharField U_LINUART_BRR2 @0x5243;//Baud Rate Register 2
ext volatile UCharField U_LINUART_CR1 @0x5244;//Control Register 1
ext volatile UCharField U_LINUART_CR2 @0x5245;//Control Register 2
ext volatile UCharField U_LINUART_CR3 @0x5246;//Control Register 3
ext volatile UCharField U_LINUART_CR4 @0x5247;//Control Register 4
ext volatile UCharField U_LINUART_CR5 @0x5249;//Control Register 5
#define LINUART_SR                  U_LINUART_SR.byte
#define LINUART_DR                  U_LINUART_DR.byte
#define LINUART_BRR1                U_LINUART_BRR1.byte
#define LINUART_BRR2                U_LINUART_BRR2.byte
#define LINUART_CR1                 U_LINUART_CR1.byte
#define LINUART_CR2                 U_LINUART_CR2.byte
#define LINUART_CR3                 U_LINUART_CR3.byte
#define LINUART_CR4                 U_LINUART_CR4.byte
#define LINUART_CR5                 U_LINUART_CR5.byte




//TIM1
ext volatile UCharField U_TIM1_CR1 @0x5250;  //Control Register 1
ext volatile UCharField U_TIM1_CR2 @0x5251;  //Control Register 2
ext volatile UCharField U_TIM1_SMCR @0x5252; //Slave Mode Control Register
ext volatile UCharField U_TIM1_ETR @0x5253;  //external Trigger Register
ext volatile UCharField U_TIM1_IER @0x5254;  //Interrupt Enable Register
ext volatile UCharField U_TIM1_SR1 @0x5255;  //Status Register 1
ext volatile UCharField U_TIM1_SR2 @0x5256;  //Status Register 2
ext volatile UCharField U_TIM1_EGR @0x5257;  //Event Generation Register
ext volatile UCharField U_TIM1_CCMR1 @0x5258;//Capture/Compare Mode Register 1
ext volatile UCharField U_TIM1_CCMR2 @0x5259;//Capture/Compare Mode Register 2
ext volatile UCharField U_TIM1_CCMR3 @0x525A;//Capture/Compare Mode Register 3
ext volatile UCharField U_TIM1_CCMR4 @0x525B;//Capture/Compare Mode Register 4
ext volatile UCharField U_TIM1_CCER1 @0x525C;//Capture/Compare Enable Register 1
ext volatile UCharField U_TIM1_CCER2 @0x525D;//Capture/Compare Enable Register 2
ext volatile UCharField U_TIM1_CNTRH @0x525E;//Counter High
ext volatile UCharField U_TIM1_CNTRL @0x525F;//Counter Low
ext volatile UCharField U_TIM1_PSCRH @0x5260;//Prescaler high
ext volatile UCharField U_TIM1_PSCRL @0x5261;//Prescaler Low
ext volatile UCharField U_TIM1_ARRH @0x5262; //Auto-Reload Register High
ext volatile UCharField U_TIM1_ARRL @0x5263; //Auto-Reload Register Low
ext volatile UCharField U_TIM1_RCR @0x5264;  //Repetition Counter Register
ext volatile UCharField U_TIM1_CCR1H @0x5265;//Capture/Compare Register 1 High
ext volatile UCharField U_TIM1_CCR1L @0x5266;//Capture/Compare Register 1 Low
ext volatile UCharField U_TIM1_CCR2H @0x5267;//Capture/Compare Register 2 High
ext volatile UCharField U_TIM1_CCR2L @0x5268;//Capture/Compare Register 2 Low
ext volatile UCharField U_TIM1_CCR3H @0x5269;//Capture/Compare Register 3 High
ext volatile UCharField U_TIM1_CCR3L @0x526A;//Capture/Compare Register 3 Low
ext volatile UCharField U_TIM1_CCR4H @0x526B;//Capture/Compare Register 4 High
ext volatile UCharField U_TIM1_CCR4L @0x526C;//Capture/Compare Register 4 Low
ext volatile UCharField U_TIM1_BKR @0x526D;  //Break Register
ext volatile UCharField U_TIM1_DTR @0x526E;  //Dead-Time Register
ext volatile UCharField U_TIM1_OISR @0x526F; //Output Idle State Register
#define TIM1_CR1                        U_TIM1_CR1.byte
#define TIM1_CR1_CEN                     U_TIM1_CR1.field.B0
#define TIM1_CR1_UDIS                   U_TIM1_CR1.field.B1
#define TIM1_CR1_URS                     U_TIM1_CR1.field.B2
#define TIM1_CR1_OPM                    U_TIM1_CR1.field.B3
#define TIM1_CR1_DIR                     U_TIM1_CR1.field.B4
#define TIM1_CR1_ARPE                   U_TIM1_CR1.field.B7

#define TIM1_CR2                        U_TIM1_CR2.byte
#define TIM1_SMCR                       U_TIM1_SMCR.byte
#define TIM1_ETR                        U_TIM1_ETR.byte
#define TIM1_IER                        U_TIM1_IER.byte
#define TIM1_SR1                        U_TIM1_SR1.byte

#define TIM1_SR1_UIF                    U_TIM1_SR1.field.B0
#define TIM1_SR1_IC1IF                U_TIM1_SR1.field.B1
#define TIM1_SR1_IC2IF                U_TIM1_SR1.field.B2
#define TIM1_SR1_IC3IF                U_TIM1_SR1.field.B3
#define TIM1_SR1_IC4IF                U_TIM1_SR1.field.B4
#define TIM1_SR1_COMIF               U_TIM1_SR1.field.B5
#define TIM1_SR1_TIF                    U_TIM1_SR1.field.B6
#define TIM1_SR1_BIF                    U_TIM1_SR1.field.B7

#define TIM1_SR1_OC1IF	           TIM1_SR1_IC1IF
#define TIM1_SR1_OC2IF	           TIM1_SR1_IC2IF
#define TIM1_SR1_OC3IF	           TIM1_SR1_IC3IF
#define TIM1_SR1_OC4IF	           TIM1_SR1_IC4IF

#define TIM1_SR2                        U_TIM1_SR2.byte
#define TIM1_SR2_CC1OF            U_TIM2_SR2.field.B1
#define TIM1_SR2_CC2OF            U_TIM2_SR2.field.B2
#define TIM1_SR2_CC3OF            U_TIM2_SR2.field.B3
#define TIM1_SR2_CC4OF            U_TIM2_SR2.field.B4

#define TIM1_EGR                        U_TIM1_EGR.byte
#define TIM1_CCMR1                      U_TIM1_CCMR1.byte
#define TIM1_CCMR2                      U_TIM1_CCMR2.byte
#define TIM1_CCMR3                      U_TIM1_CCMR3.byte
#define TIM1_CCMR4				U_TIM1_CCMR4.byte
#define TIM1_CCER1                      U_TIM1_CCER1.byte
#define TIM1_CCER2                      U_TIM1_CCER2.byte
#define TIM1_CNTRH                      U_TIM1_CNTRH.byte
#define TIM1_CNTRL                      U_TIM1_CNTRL.byte
#define TIM1_PSCRH                      U_TIM1_PSCRH.byte
#define TIM1_PSCRL                      U_TIM1_PSCRL.byte
#define TIM1_ARRH                       U_TIM1_ARRH.byte
#define TIM1_ARRL                       U_TIM1_ARRL.byte
#define TIM1_RCR                        U_TIM1_RCR.byte
#define TIM1_CCR1H                      U_TIM1_CCR1H.byte
#define TIM1_CCR1L                      U_TIM1_CCR1L.byte
#define TIM1_CCR2H                      U_TIM1_CCR2H.byte
#define TIM1_CCR2L                      U_TIM1_CCR2L.byte
#define TIM1_CCR3H                      U_TIM1_CCR3H.byte
#define TIM1_CCR3L                      U_TIM1_CCR3L.byte
#define TIM1_CCR4H                      U_TIM1_CCR4H.byte
#define TIM1_CCR4L                      U_TIM1_CCR4L.byte
#define TIM1_BKR                        U_TIM1_BKR.byte
#define TIM1_DTR                        U_TIM1_DTR.byte
#define TIM1_OISR                       U_TIM1_OISR.byte


//TIM2
ext volatile UCharField U_TIM2_CR1 @0x5300;
ext volatile UCharField U_TIM2_IER @0x5301;
ext volatile UCharField U_TIM2_SR1 @0x5302;
ext volatile UCharField U_TIM2_SR2 @0x5303;
ext volatile UCharField U_TIM2_EGR @0x5304;
ext volatile UCharField U_TIM2_CCMR1 @0x5305;
ext volatile UCharField U_TIM2_CCMR2 @0x5306;
ext volatile UCharField U_TIM2_CCMR3 @0x5307;
ext volatile UCharField U_TIM2_CCER1 @0x5308;
ext volatile UCharField U_TIM2_CCER2 @0x5309;
ext volatile UCharField U_TIM2_CNTRH @0x530A;
ext volatile UCharField U_TIM2_CNTRL @0x530B;
ext volatile UCharField U_TIM2_PSCR @0x530C;
ext volatile UCharField U_TIM2_ARRH @0x530D;
ext volatile UCharField U_TIM2_ARRL @0x530E;
ext volatile UCharField U_TIM2_CCR1H @0x530F;
ext volatile UCharField U_TIM2_CCR1L @0x5310;
ext volatile UCharField U_TIM2_CCR2H @0x5311;
ext volatile UCharField U_TIM2_CCR2L @0x5312;
ext volatile UCharField U_TIM2_CCR3H @0x5313;
ext volatile UCharField U_TIM2_CCR3L @0x5314;
#define TIM2_CR1                        U_TIM2_CR1.byte
#define TIM2_CR1_CEN                    U_TIM2_CR1.field.B0
#define TIM2_CR1_UDIS                   U_TIM2_CR1.field.B1
#define TIM2_CR1_URS                    U_TIM2_CR1.field.B2
#define TIM2_CR1_OPM                    U_TIM2_CR1.field.B3
#define TIM2_CR1_ARPE                   U_TIM2_CR1.field.B7


#define TIM2_IER                        U_TIM2_IER.byte
#define TIM2_IER_UIE                    U_TIM2_IER.field.B0
#define TIM2_IER_CC1IE                  U_TIM2_IER.field.B1
#define TIM2_IER_CC2IE                  U_TIM2_IER.field.B2
#define TIM2_IER_CC3IE                  U_TIM2_IER.field.B3


#define TIM2_SR1                        U_TIM2_SR1.byte
#define TIM2_SR1_UIF                    U_TIM2_SR1.field.B0
#define TIM2_SR1_IC1IF                  U_TIM2_SR1.field.B1
#define TIM2_SR1_IC2IF                  U_TIM2_SR1.field.B2
#define TIM2_SR1_IC3IF                  U_TIM2_SR1.field.B3
#define TIM2_SR1_TIF                    U_TIM2_SR1.field.B6

#define TIM2_SR1_OC1IF               TIM2_SR1_IC1IF
#define TIM2_SR1_OC2IF               TIM2_SR1_IC2IF
#define TIM2_SR1_OC3IF               TIM2_SR1_IC3IF

#define TIM2_SR2                        U_TIM2_SR2.byte
#define TIM2_SR2_CC1OF                  U_TIM2_SR2.field.B1
#define TIM2_SR2_CC2OF                  U_TIM2_SR2.field.B2
#define TIM2_SR2_CC3OF                  U_TIM2_SR2.field.B3

#define TIM2_EGR                        U_TIM2_EGR.byte
#define TIM2_EGR_UG                     U_TIM2_EGR.field.B0
#define TIM2_EGR_CC1G                   U_TIM2_EGR.field.B1
#define TIM2_EGR_CC2G                   U_TIM2_EGR.field.B2
#define TIM2_EGR_CC3G                   U_TIM2_EGR.field.B3
#define TIM2_EGR_TG                     U_TIM2_EGR.field.B6

#define TIM2_CCMR1                      U_TIM2_CCMR1.byte
#define TIM2_CCMR2                      U_TIM2_CCMR2.byte
#define TIM2_CCMR3                      U_TIM2_CCMR3.byte
#define TIM2_CCER1                      U_TIM2_CCER1.byte
#define TIM2_CCER1_CC1E                 U_TIM2_CCER1.field.B0
#define TIM2_CCER1_CC1P                 U_TIM2_CCER1.field.B1
#define TIM2_CCER1_CC2E                 U_TIM2_CCER1.field.B4
#define TIM2_CCER1_CC2P                 U_TIM2_CCER1.field.B5

#define TIM2_CCER2                      U_TIM2_CCER2.byte
#define TIM2_CCER2_CC3E                 U_TIM2_CCER2.field.B0
#define TIM2_CCER2_CC3P                 U_TIM2_CCER2.field.B1

#define TIM2_CNTRH                      U_TIM2_CNTRH.byte
#define TIM2_CNTRL                      U_TIM2_CNTRL.byte
#define TIM2_PSCR                       U_TIM2_PSCR.byte
#define TIM2_ARRH                       U_TIM2_ARRH.byte
#define TIM2_ARRL                       U_TIM2_ARRL.byte
#define TIM2_CCR1H                      U_TIM2_CCR1H.byte
#define TIM2_CCR1L                      U_TIM2_CCR1L.byte
#define TIM2_CCR2H                      U_TIM2_CCR2H.byte
#define TIM2_CCR2L                      U_TIM2_CCR2L.byte
#define TIM2_CCR3H                      U_TIM2_CCR3H.byte
#define TIM2_CCR3L                      U_TIM2_CCR3L.byte

//TIM3
ext volatile UCharField U_TIM3_CR1 @0x5320;
ext volatile UCharField U_TIM3_IER @0x5321;
ext volatile UCharField U_TIM3_SR1 @0x5322;
ext volatile UCharField U_TIM3_SR2 @0x5323;
ext volatile UCharField U_TIM3_EGR @0x5324;
ext volatile UCharField U_TIM3_CCMR1 @0x5325;
ext volatile UCharField U_TIM3_CCMR2 @0x5326;
ext volatile UCharField U_TIM3_CCER1 @0x5327;
ext volatile UCharField U_TIM3_CNTRH @0x5328;
ext volatile UCharField U_TIM3_CNTRL @0x5329;
ext volatile UCharField U_TIM3_PSCR @0x532A;
ext volatile UCharField U_TIM3_ARRH @0x532B;
ext volatile UCharField U_TIM3_ARRL @0x532C;
ext volatile UCharField U_TIM3_CCR1H @0x532D;
ext volatile UCharField U_TIM3_CCR1L @0x532E;
ext volatile UCharField U_TIM3_CCR2H @0x532F;
ext volatile UCharField U_TIM3_CCR2L @0x5330;

#define TIM3_CR1                        U_TIM3_CR1.byte
#define TIM3_CR1_CEN                U_TIM3_CR1.field.B0
#define TIM3_CR1_UDIS              U_TIM3_CR1.field.B1
#define TIM3_CR1_URS                 U_TIM3_CR1.field.B2
#define TIM3_CR1_OPM                 U_TIM3_CR1.field.B3
#define TIM3_CR1_ARPE                U_TIM3_CR1.field.B7


#define TIM3_ETR                        U_TIM3_ETR.byte
#define TIM3_IER                        U_TIM3_IER.byte
#define TIM3_IER_UIE                    U_TIM3_IER.field.B0
#define TIM3_IER_CC1IE                  U_TIM3_IER.field.B1
#define TIM3_IER_CC2IE                  U_TIM3_IER.field.B2
#define TIM3_IER_CC3IE                  U_TIM3_IER.field.B3

#define TIM3_SR1                        U_TIM3_SR1.byte
#define TIM3_SR1_UIF                    U_TIM3_SR1.field.B0
#define TIM3_SR1_CC1IF                  U_TIM3_SR1.field.B1
#define TIM3_SR1_CC2IF                  U_TIM3_SR1.field.B2
#define TIM3_SR1_CC3IF                  U_TIM3_SR1.field.B3
#define TIM3_SR1_TIF                    U_TIM3_SR1.field.B6

#define TIM3_SR2                        U_TIM3_SR2.byte
#define TIM3_SR2_CC1OF                  U_TIM3_SR2.field.B1
#define TIM3_SR2_CC2OF                  U_TIM3_SR2.field.B2
#define TIM3_SR2_CC3OF                  U_TIM3_SR2.field.B3


#define TIM3_EGR                        U_TIM3_EGR.byte
#define TIM3_EGR_UG                     U_TIM3_EGR.field.B0
#define TIM3_EGR_CC1G                   U_TIM3_EGR.field.B1
#define TIM3_EGR_CC2G                   U_TIM3_EGR.field.B2
#define TIM3_EGR_CC3G                   U_TIM3_EGR.field.B3
#define TIM3_EGR_TG                     U_TIM3_EGR.field.B6

#define TIM3_CCMR1                      U_TIM3_CCMR1.byte
#define TIM3_CCMR2                      U_TIM3_CCMR2.byte
#define TIM3_CCER1			     		U_TIM3_CCER1.byte
#define TIM3_CCER1_CC1E                 U_TIM3_CCER1.field.B0
#define TIM3_CCER1_CC1P                 U_TIM3_CCER1.field.B1
#define TIM3_CCER1_CC2E                 U_TIM3_CCER1.field.B4
#define TIM3_CCER1_CC2P                 U_TIM3_CCER1.field.B5

#define TIM3_CNTRH                      	U_TIM3_CNTRH.byte
#define TIM3_CNTRL                      U_TIM3_CNTRL.byte
#define TIM3_PSCR                       U_TIM3_PSCR.byte
#define TIM3_ARRH                       U_TIM3_ARRH.byte
#define TIM3_ARRL                       U_TIM3_ARRL.byte
#define TIM3_CCR1H                      U_TIM3_CCR1H.byte
#define TIM3_CCR1L                      U_TIM3_CCR1L.byte
#define TIM3_CCR2H                      U_TIM3_CCR2H.byte
#define TIM3_CCR2L                      U_TIM3_CCR2L.byte
#define TIM3_CCR3H                      U_TIM3_CCR3H.byte
#define TIM3_CCR3L                      U_TIM3_CCR3L.byte

//TIM4
ext volatile UCharField U_TIM4_CR1 	@0x5340;//TIM4 Control register1
ext volatile UCharField U_TIM4_IER 	@0x5341;//TIM4 interrupt enable register
ext volatile UCharField U_TIM4_SR	 @0x5342;//TIM4 status register
ext volatile UCharField U_TIM4_EGR 	@0x5343;//TIM4 Event Generation register
ext volatile UCharField U_TIM4_CNTR	 @0x5344;//TIM4 Counter
ext volatile UCharField U_TIM4_PSCR	 @0x5345;//TIM4 Prescaler register
ext volatile UCharField U_TIM4_ARR 	@0x5346;//TIM4 Auto-reload register
#define TIM4_CR1                       U_TIM4_CR1.byte
#define TIM4_CR1_CEN               U_TIM4_CR1.field.B0 //Counter Enable.
#define TIM4_CR1_UDIS             U_TIM4_CR1.field.B1 //Update Disable.
#define TIM4_CR1_URS               U_TIM4_CR1.field.B2 //Update Request Source.
#define TIM4_CR1_OPM               U_TIM4_CR1.field.B3 //One Pulse Mode.
#define TIM4_CR1_ARPE             U_TIM4_CR1.field.B7 //Auto-Reload Preload Enable.

#define TIM4_IER                       U_TIM4_IER.byte
#define TIM4_IER_UIE                U_TIM4_IER.field.B0 //Update Interrupt Enable.

#define TIM4_SR                        U_TIM4_SR.byte
#define TIM4_SR_UIF                U_TIM4_SR.field.B0 //Update Interrupt Flag.

#define TIM4_EGR                       U_TIM4_EGR.byte
#define TIM4_EGR_UG                U_TIM4_EGR.field.B0  //Update Generation.

#define TIM4_CNTR                      U_TIM4_CNTR.byte
#define TIM4_PSCR                      U_TIM4_PSCR.byte
#define TIM4_ARR                       U_TIM4_ARR.byte


//ADC
ext volatile UCharField U_ADC_CSR	 @0x5400;//ADC Control/Status Register
ext volatile UCharField U_ADC_CR1 	@0x5401;//ADC configuration 1 
ext volatile UCharField U_ADC_CR2 	@0x5402;//ADC configuration 2
ext volatile UCharField U_ADC_CR3	 @0x5403;//ADC configuration 3
ext volatile UCharField U_ADC_DRH 	@0x5404;//ADC Data Register High
ext volatile UCharField U_ADC_DRL 	@0x5405;//ADC Data Register Low
ext volatile UCharField U_ADC_TDRH 	@0x5406;//ADC Schmitt Trigger Disable Register High
ext volatile UCharField U_ADC_TDRL 	@0x5407;//ADC Schmitt Trigger Disable Register Low
#define AIN0		0
#define AIN1		1
#define AIN2		2
#define AIN3		3
#define AIN4		4
#define AIN5		5
#define AIN6		6
#define AIN7		7
#define AIN8		8
#define AIN9		9
#define AIN10		10
#define AIN11		11
#define AIN12		12
#define AIN13		13
#define AIN14		14
#define AIN15		15

#define ADC_CSR                       U_ADC_CSR.byte
#define ADC_CSR_ITEN             U_ADC_CSR.field.B5 //Interrupt enable for EOC
#define ADC_CSR_EOC              U_ADC_CSR.field.B7 //End of conversion

#define ADC_CR1                       U_ADC_CR1.byte
#define ADC_CR1_ADON            U_ADC_CR1.field.B0 //A/D Converter on/off
#define ADC_CR1_CONT             U_ADC_CR1.field.B1 //Continuous conversion


#define ADC_CR2                       U_ADC_CR2.byte
#define ADC_CR2_ALIGN           U_ADC_CR2.field.B3 //Data alignment
#define ADC_CR2_EXTTRIG       U_ADC_CR2.field.B6 //External trigger enable

#define ADC_CR3                       U_ADC_CR3.byte
#define ADC_DRH                       U_ADC_DRH.byte
#define ADC_DRL                       U_ADC_DRL.byte
#define ADC_TDRH                      U_ADC_TDRH.byte
#define ADC_TDRL                      U_ADC_TDRL.byte



//CAN
ext volatile UCharField U_CAN_MCR @0x5420;//CAN Master Control register
ext volatile UCharField U_CAN_MSR @0x5421;//CAN Master Status register
ext volatile UCharField U_CAN_TSR @0x5422;//CAN Transmit Status register
ext volatile UCharField U_CAN_TPR @0x5423;//CAN Transmit Priority register
ext volatile UCharField U_CAN_RFR @0x5424;//CAN Receive FIFO register
ext volatile UCharField U_CAN_IER @0x5425;//CAN Interrupt Enable register
ext volatile UCharField U_CAN_DGR @0x5426;//CAN Diagnosis register
ext volatile UCharField U_CAN_FPSR @0x5427;//CAN Page Selection register
ext volatile UCharField U_CAN_P0 @0x5428;//CAN Page Register 0
ext volatile UCharField U_CAN_P1 @0x5429;//CAN Page Register 1
ext volatile UCharField U_CAN_P2 @0x542A;//CAN Page Register 2
ext volatile UCharField U_CAN_P3 @0x542B;//CAN Page Register 3
ext volatile UCharField U_CAN_P4 @0x542C;//CAN Page Register 4
ext volatile UCharField U_CAN_P5 @0x542D;//CAN Page Register 5
ext volatile UCharField U_CAN_P6 @0x542E;//CAN Page Register 6
ext volatile UCharField U_CAN_P7 @0x542F;//CAN Page Register 7
ext volatile UCharField U_CAN_P8 @0x5430;//CAN Page Register 8
ext volatile UCharField U_CAN_P9 @0x5431;//CAN Page Register 9
ext volatile UCharField U_CAN_PA @0x5432;//CAN Page Register A
ext volatile UCharField U_CAN_PB @0x5433;//CAN Page Register B
ext volatile UCharField U_CAN_PC @0x5434;//CAN Page Register C
ext volatile UCharField U_CAN_PD @0x5435;//CAN Page Register D
ext volatile UCharField U_CAN_PE @0x5436;//CAN Page Register E
ext volatile UCharField U_CAN_PF @0x5437;//CAN Page Register F
#define CAN_MCR                       U_CAN_MCR.byte
#define CAN_MSR                       U_CAN_MSR.byte
#define CAN_TSR                       U_CAN_TSR.byte
#define CAN_TPR                       U_CAN_TPR.byte
#define CAN_RFR                       U_CAN_RFR.byte
#define CAN_IER                       U_CAN_IER.byte
#define CAN_DGR                      U_CAN_DGR.byte
#define CAN_FPSR                    U_CAN_FPSR.byte
#define CAN_P0                        U_CAN_P0.byte
#define CAN_P1                        U_CAN_P1.byte
#define CAN_P2                        U_CAN_P2.byte
#define CAN_P3                        U_CAN_P3.byte
#define CAN_P4                        U_CAN_P4.byte
#define CAN_P5                        U_CAN_P5.byte
#define CAN_P6                        U_CAN_P6.byte
#define CAN_P7                        U_CAN_P7.byte
#define CAN_P8                        U_CAN_P8.byte
#define CAN_P9                        U_CAN_P9.byte
#define CAN_PA                        U_CAN_PA.byte
#define CAN_PB                        U_CAN_PB.byte
#define CAN_PC                        U_CAN_PC.byte
#define CAN_PD                        U_CAN_PD.byte
#define CAN_PE                        U_CAN_PE.byte
#define CAN_PF                        U_CAN_PF.byte


/*  Tx MailBox / Receive FIFO Registers */
ext volatile UCharField U_CAN_MCSR		@0x5428;
ext volatile UCharField U_CAN_MFMI		@0x5428;
ext volatile UCharField U_CAN_MDLC		@0x5429;
ext volatile UCharField U_CAN_MIDR1		@0x542a;
ext volatile UCharField U_CAN_MIDR2		@0x542b;
ext volatile UCharField U_CAN_MIDR3		@0x542c;
ext volatile UCharField U_CAN_MIDR4		@0x542d;
//ext volatile UCharField U_CAN_MDAR[8]	@0x542e;
ext volatile UCharField U_CAN_MTSLR		@0x5436;
ext volatile UCharField U_CAN_MTSHR		@0x5437;
ext volatile UCharField U_CAN_MIDR12	@0x542a;
ext volatile UCharField U_CAN_MIDR34	@0x542c;
volatile unsigned char CAN_MDAR[8]	@0x542e;
#define CAN_MCSR                        U_CAN_MCSR.byte
#define CAN_MFMI                        U_CAN_MFMI.byte
#define CAN_MDLC                        U_CAN_MDLC.byte
#define CAN_MIDIR1                     U_CAN_MIDIR1.byte
#define CAN_MIDIR2                     U_CAN_MIDIR2.byte
#define CAN_MIDIR3                     U_CAN_MIDIR3.byte
#define CAN_MIDIR4                     U_CAN_MIDIR4.byte
#define CAN_MTSLR                      U_CAN_MTSLR.byte
#define CAN_MTSHR                      U_CAN_MTSHR.byte
#define CAN_MIDR12                     U_CAN_MIDR12.byte
#define CAN_MIDR34                     U_CAN_MIDR34.byte


/*  Configuaration/Diagnosis Registers */
ext volatile UCharField U_CAN_ESR  	@0x5428;
ext volatile UCharField U_CAN_EIER 	@0x5429;
ext volatile UCharField U_CAN_TECR  	@0x542a;
ext volatile UCharField U_CAN_RECR  	@0x542b;
ext volatile UCharField U_CAN_BTR1 	@0x542c;
ext volatile UCharField U_CAN_BTR2 	@0x542d;
ext volatile UCharField U_CAN_FMR1 	@0x5430;
ext volatile UCharField U_CAN_FMR2 	@0x5431;
ext volatile UCharField U_CAN_FCR1 	@0x5432;
ext volatile UCharField U_CAN_FCR2 	@0x5433;
ext volatile UCharField U_CAN_FCR3 	@0x5434;
#define CAN_ESR                   U_CAN_ESR.byte
#define CAN_EIER                 U_CAN_EIER.byte
#define CAN_TECR                 U_CAN_TECR.byte
#define CAN_RECR                 U_CAN_RECR.byte
#define CAN_BTR1                 U_CAN_BTR1.byte
#define CAN_BTR2                 U_CAN_BTR2.byte
#define CAN_FMR1                 U_CAN_FMR1.byte
#define CAN_FMR2                 U_CAN_FMR2.byte
#define CAN_FCR1                 U_CAN_FCR1.byte
#define CAN_FCR2                 U_CAN_FCR2.byte
#define CAN_FCR3                 U_CAN_FCR3.byte





/*  Acceptance filter 0:1 Registers */
ext volatile UCharField U_CAN_FxR0 	@0x5428;
ext volatile UCharField U_CAN_FxR1 	@0x5429;
ext volatile UCharField U_CAN_FxR2 	@0x542a;
ext volatile UCharField U_CAN_FxR3 	@0x542b;
ext volatile UCharField U_CAN_FxR4 	@0x542c;
ext volatile UCharField U_CAN_FxR5 	@0x542d;
ext volatile UCharField U_CAN_FxR6 	@0x542e;
ext volatile UCharField U_CAN_FxR7 	@0x542f;
ext volatile UCharField U_CAN_FyR0 	@0x5430;
ext volatile UCharField U_CAN_FyR1 	@0x5431;
ext volatile UCharField U_CAN_FyR2 	@0x5432;
ext volatile UCharField U_CAN_FyR3 	@0x5433;
ext volatile UCharField U_CAN_FyR4 	@0x5434;
ext volatile UCharField U_CAN_FyR5 	@0x5435;
ext volatile UCharField U_CAN_FyR6 	@0x5436;
ext volatile UCharField U_CAN_FyR7 	@0x5437;
#define CAN_FxR0                 U_CAN_FxR0.byte
#define CAN_FxR1                 U_CAN_FxR1.byte
#define CAN_FxR2                 U_CAN_FxR2.byte
#define CAN_FxR3                 U_CAN_FxR3.byte
#define CAN_FxR4                 U_CAN_FxR4.byte
#define CAN_FxR5                 U_CAN_FxR5.byte
#define CAN_FxR6                 U_CAN_FxR6.byte
#define CAN_FxR7                 U_CAN_FxR7.byte
#define CAN_FyR0                 U_CAN_FyR0.byte
#define CAN_FyR1                 U_CAN_FyR1.byte
#define CAN_FyR2                 U_CAN_FyR2.byte
#define CAN_FyR3                 U_CAN_FyR3.byte
#define CAN_FyR4                 U_CAN_FyR4.byte
#define CAN_FyR5                 U_CAN_FyR5.byte
#define CAN_FyR6                 U_CAN_FyR6.byte
#define CAN_FyR7                 U_CAN_FyR7.byte




//CPU
ext volatile UCharField U_CPU_A @0x7F00; //Accumulater
ext volatile UCharField U_CPU_PCE @0x7F01;//Program counter extended
ext volatile UCharField U_CPU_PCH @0x7F02;//Program counter high
ext volatile UCharField U_CPU_PCL @0x7F03;//Program counter low
ext volatile UCharField U_CPU_XH @0x7F04;//X index register high
ext volatile UCharField U_CPU_XL @0x7F05;//X index register low
ext volatile UCharField U_CPU_YH @0x7F06;//Y index register high
ext volatile UCharField U_CPU_YL @0x7F07;//Y index register low
ext volatile UCharField U_CPU_SPH @0x7F08;//Stack pointer high
ext volatile UCharField U_CPU_SPL @0x7F09;//Stack pointer low
ext volatile UCharField U_CPU_CCR @0x7F0A;//condition code register
#define CPU_A                        U_CPU_A.byte
#define CPU_PCE                      U_CPU_PCE.byte
#define CPU_PCH                      U_CPU_PCH.byte
#define CPU_PCL                      U_CPU_PCL.byte
#define CPU_XH                       U_CPU_XH.byte
#define CPU_XL                       U_CPU_XL.byte
#define CPU_YH                       U_CPU_YH.byte
#define CPU_YL                       U_CPU_YL.byte
#define CPU_SPH                      U_CPU_SPH.byte
#define CPU_SPL                      U_CPU_SPL.byte
#define CPU_CCR                      U_CPU_CCR.byte


//CORE
ext volatile UCharField U_CFG_GCR @0x7F60;//core configuration register
#define CFG_GCR                          U_CFG_GCR.byte
//ITC
ext volatile UCharField U_ITC_SPR1 @0x7F70;//Interrupt Software priority register 1
ext volatile UCharField U_ITC_SPR2 @0x7F71;//Interrupt Software priority register 2
ext volatile UCharField U_ITC_SPR3 @0x7F72;//Interrupt Software priority register 3
ext volatile UCharField U_ITC_SPR4 @0x7F73;//Interrupt Software priority register 4
ext volatile UCharField U_ITC_SPR5 @0x7F74;//Interrupt Software priority register 5
ext volatile UCharField U_ITC_SPR6 @0x7F75;//Interrupt Software priority register 6
ext volatile UCharField U_ITC_SPR7 @0x7F76;//Interrupt Software priority register 7
ext volatile UCharField U_ITC_SPR8 @0x7F77;//Interrupt Software priority register 8
#define ITC_SPR1                      U_ITC_SPR1.byte
#define ITC_SPR2                      U_ITC_SPR2.byte
#define ITC_SPR3                      U_ITC_SPR3.byte
#define ITC_SPR4                      U_ITC_SPR4.byte
#define ITC_SPR5                      U_ITC_SPR5.byte
#define ITC_SPR6                      U_ITC_SPR6.byte
#define ITC_SPR7                      U_ITC_SPR7.byte
#define ITC_SPR8                      U_ITC_SPR8.byte


//SWIN
ext volatile UCharField U_SWIM_CSR @0x7F80;//SWIM control status register
#define SWIM_CSR                      U_SWIM_CSR.byte

//CPU/SWIM/debug module/interrupt controller registers (continued)
ext volatile UCharField U_DM_BK1RE @0x7F90;
ext volatile UCharField U_DM_BK1RH @0x7F91;
ext volatile UCharField U_DM_BK1RL @0x7F92;
ext volatile UCharField U_DM_BK2RE @0x7F93;
ext volatile UCharField U_DM_BK2RH @0x7F94;
ext volatile UCharField U_DM_BK2RL @0x7F95;
ext volatile UCharField U_DM_CR1 @0x7F96;
ext volatile UCharField U_DM_CR2 @0x7F97;
ext volatile UCharField U_DM_CSR1 @0x7F98;
ext volatile UCharField U_DM_CSR2 @0x7F99;
ext volatile UCharField U_DM_ENFCTR @0x7F9A;

#define DM_BK1RE			U_DM_BK1RE.byte
#define DM_BK1RH			U_DM_BK1RH.byte
#define DM_BK1RL			U_DM_BK1RL.byte
#define DM_BK2RE			U_DM_BK2RE.byte
#define DM_BK2RH			U_DM_BK2RH.byte
#define DM_BK2RL			U_DM_BK2RL.byte
#define DM_CR1				U_DM_CR1.byte
#define DM_CR2				U_DM_CR2.byte
#define DM_CSR1				U_DM_CSR1.byte
#define DM_CSR2				U_DM_CSR2.byte
#define DM_ENFCTR			U_DM_ENFCTR.byte


ext volatile unsigned char EEPROMBuff[2048] @0x4000; 


/******************************************************************************/
